Chip Multiprocessor Architecture

After a discussion of the basic pros and cons of chip multiprocessors (CMPs) when they are compared with conventional uniprocessors, this book examines how CMPs can best be designed to handle two radically different kinds of workloads that are likely to be used with a CMP: highly parallel, throughput-sensitive applications at one end of the spectrum. and less parallel, latency-sensitive applications at the other. This book discusses many techniques that can be used in CMPs to simplify parallel programming, with an emphasis on research directions proposed at Stanford University. To illustrate the advantages possible with a CMP using a couple of solid examples, extra focus is given to thread-level speculation (TLS), a way to automatically break up nominally sequential applications into parallel threads on a CMP, and transactional memory. This model can greatly simplify manual parallel programming by using hardware - instead of conventional software locks - to enforce atomic code execution of blocks of instructions, a technique that makes parallel coding much less error-prone.

ISBN 159829122X   Volumes 1 ISBN13 9781598291223 (What's this?)   Weight (grammes) 281 Publisher Morgan & Claypool Publishers   Published in San Rafael Imprint Morgan & Claypool Publishers   Series ISSN 1935-323 Format Paperback   Series title Synthesis Lectures on Computer Architecture Publication date 15 Oct 2007   Height (mm) 235 Library of Congress QA   Width (mm) 190 DEWEY 004.22   Spine width (mm) 8 DEWEY edition DC22   Academic level Professional / Scholarly Pages 145

1		The Case for CMPs		1
2		Improving Throughput		21
3		Improving Latency Automatically		61
4		Improving Latency Using Manual Parallel Programming		103
5		A Multicore World: The Future of CMPs		141

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